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ST10C167
16-BIT MCU WITH 32K BYTE ROM
s
HIGH PERFORMANCE CPU - 16-BIT CPU WITH 4-STAGE PIPELINE - 80ns INSTRUCTION CYCLE TIME @ 25MHz CLK - 400ns 16 X 16-BIT MULTIPLICATION - 800ns 32 / 16-BIT DIVISION - ENHANCE D BOOLEAN BIT MANIPULATION FACILITIES - ADDITIONAL INSTRUCTIONS TO SUPPOR T HLL AND OPERATING SYSTEMS - SINGLE-CYCL E CONT EXT SWITCHING SUPPORT MEMORY ORGANIZATION - 32K BYTE ON-CHIP ROM MEMORY - UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN) - 2K BYTE ON-CHIP INTERNAL RAM (IRAM) - 2K BYTE ON-CHIP EXTENSION RAM (XRAM) FAST AND FLEXIBLE BUS - PROGRAMMABLE EXTERNAL BUS CHARA CTERISTICS FOR DIFFERENT ADDRESS RANGES - 8-BIT OR 16-BIT EXTERNAL DATA BUS - MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRE SS/DATA BUSES - FIVE PROGRAMMABLE CHIP-SELECT SIGNALS - HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT INTERRUPT - 8-CHANNEL PERIPHERAL EVENT CONTROLLER FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA TRANSFER - 16-PRIORITY-LEVEL INTERRUPT SYSTE M WITH 56 SOURCES, SAMPLE-RATE DOWN TO 40ns TIMERS - TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS - TWO 16-CHANNEL CAPTURE/COMPARE UNITS A/D CONVERTER - 16-CHANN EL 10-BIT - 7.76s CONVERSION TIME FAIL-SAFE PROTECTION - PROGRAMMABLE WATCHDOG TIMER - OSCILLATOR WATCHDOG ON-CHIP CAN 2.0B INTERFACE ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL - DIRECT OR PRESCALE D CLOCK INPUT
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PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack)
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s
s s s s
s
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UP TO 111 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIA L FUNCTION - PROGRAMMABLE DRIVE STRENGTH - PROGRAMMABLE THRESHOLD (HYSTERESIS) IDLE AND POWER DOWN MODES - IDLE CURRENT <95mA - POWER-DOWN SUPPLY CURRENT <400A 4-CHANNEL PWM UNIT SERIAL CHANNELS - SYNCHRONOUS/ASYN CSERIAL CHANNEL - HIGH-SPEED SYNCHRON OUS CHANNEL DEVELOPMENT SUPPORT - C-COM PILERS, MACRO-ASSEMBLER PACKAGES, EMULATORS, EVAL BOARDS, HLL-D EBUGGERS, SIMULATORS, LOGIC ANALYZER DISASSEMBLERS, PROGRAMMING BOARDS 144-PIN PQFP PACKAGE
16
s
32K Byte ROM
32
CPU-Core
16
Internal RAM
16
PEC
Watchdog
XRAM
16
s s s s s
Interrupt Controller
CAN
16
OSC.
Port 4 Port 1 Port 0
GPT1
External Bus Controller
ASC usart
10-Bit ADC
SSC
16
CAPCOM2
CAPCOM1
PWM
16
GPT2
Port 2 16 8
8
BR G Port 3 15
BR G Port 7 8 Port 8
Port 6 8
Port 5 16
August 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ST10C167
TABLE OF CONTENTS I II III IV V VI VII VIII IX IX.1 IX.2 X XI XII XIII XIV XV XVI XVII XVIII XIX XIX.1 XX XX.1 XX.2 XX.3 XX.3.1 XX.4 XX.4.1 XX.4.2
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Page 4 5 10 11 12 13 14 17 18 18 19 21 22 23 24 26 26 27 29 30 31 37 38 38 38 39 40 41 42 42
INTRODUCTION ......................................................................................................... PIN DATA .................................................................................................................. FUNCTIONAL DESCRIPTION.................................................................................... MEMORY ORGANIZATION........................................................................................ CENTRAL PROCESSING UNIT (CPU) ...................................................................... EXTERNAL BUS CONTROLLER............................................................................... INTERRUPT SYSTEM ................................................................................................ CAPTURE/COMPARE (CAPCOM) UNIT ................................................................... GENERAL PURPOSE TIMER UNIT........................................................................... GPT1 .......................................................................................................................... GPT2 .......................................................................................................................... PWM MODULE ................ ........................................................................................... PARALLEL PORTS ......... ........................................................................................... A/D CONVERTER...................................... ................................................................. SERIAL CHANNELS .............................................................................. .................... CAN MODULE ............................................................................................................ WATCHDOG TIMER................................................................................................... INSTRUCTION SET SUMMARY ............................................................................... . SYSTEM RESET......................................................................................................... POWER REDUCTION MODES .................................................................................. SPECIAL FUNCTION REGISTER OVERVIEW............ .............................................. IDENTIFICATION REGISTERS ............................................................. .................... ELECTRICAL CHARACTERISTICS ......................................................................... . ABSOLUTE MAXIMUM RATINGS ............................................................................. PARAMETER INTERPRETATION ............................................................................. DC CHARACTERISTICS ........................................................................................... A/D converter characteristics ...................................................................................... AC CHARACTERISTICS ............................................................................................ Definition of internal timing ......................................................................................... Clock generation modes .............................................................................................
ST10C167
TABLE OF CONTENTS (continued) XX.4.3 XX.4.4 XX.4.5 XX.4.6 XX.4.7 XX.4.8 XX.4.9 XX.4.10 XX.4.11 XX.4.12 XX.4.13 XXI XXII Prescaler operation .................................................................................................... Direct drive ................................................................................................................. Oscillator watchdog (OWD) ........................................................................................ Phase locked loop ...................................................................................................... Memory cycle variables .............................................................................................. External clock drive XTAL1 .......................................... .............................................. Multiplexed bus ........................................................................................................... Demultiplexed bus ...................................................................................................... CLKOUT and READY ................................................................................................. External bus arbitration ........................................................................... .................... Highspeed synchronous serial interface (SSC) timing ............................................... PACKAGE MECHANICAL DATA ........................................................................... Page 43 43 43 43 44 45 45 52 58 60 61 64 64
ORDERING INFORMATION.......................................................................................
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ST10C167
I - INTRODUCTION The ST10C167 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million Figure 1 : Logic Symbol instructions per second) with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed RAM and clock generation via PLL.
VDD
XTAL1 XTAL2 RSTIN RSTOUT RPD VAREF VAGND NMI EA READY ALE RD WR/WRL Port 5 16-bit ST10C167
VSS
Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit
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II - PIN DATA
Figure 2 : Pin Configuration (top view)
P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ST10C167
VDD VSS NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VSS VDD P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14
P0H.5/AD13 P0H.4/AD12
P0H.3/AD11 P0H.2/AD10
P0H.1/AD9
VAREF VAGND P5.10/AN10/T6EUD P5.11/AN11/T5EUD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD VSS VDD P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO VSS VDD P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IOEX2IN P2.11/CC11IOEX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN/T7IN P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VSS VDD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2AD2 P0L.A/AD1 P0L.0/AD0 EA ALE READY WR/WRL RD VSS VDD P4.7/A23 P4.6 A22/CAN_TxD P4.5 A21/CAN_RxD P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 RPD VSS VDD P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN
ST10C167
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II - PIN DATA (continued) Table 1 : Pin list
Symbol P6.0 - P6.7 Pin 1-8 Type I/O Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins have alternate functions: P6.0 ... P6.4 P6.5 P6.6 P6.7 CS0 ... CS4 HOLD HLDA BREQ Chip Select 0 Output ... Chip Select 4 Output External Master Hold Request Input Hold Acknowledge Output Bus Request Output
1 ... 5 6 7 8 P8.0 - P8.7 9 - 16
O ... O I O O I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins have alternate functions: P8.0 ... P8.7 CC16IO ... CC23IO CAPCOM2: CC16 Capture Input/Compare Output ... CAPCOM2: CC23 Capture Input/Compare Output
9 ... 16 P7.0 - P7.7 19 - 26
I/O ... I/O I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins have alternate functions: P7.0 ... P7.3 P7.4 ... P7.7 POUT0 ... POUT3 CC28IO ... CC31IO PWM Channel 0 Output ... PWM Channel 3 Output CAPCOM2: CC28 Capture Input/Compare Output ... CAPCOM2: CC31 Capture Input/Compare Output
19 ... 22 23 ... 26 P5.0 - P5.9 P5.10 - P5.15 27 - 36 39 - 44
O ... O I/O ... I/O I I
Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 16) analog input channels for the A/ D converter, where P5.x equals ANx (Analog input channel x), or they serve as timer inputs: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2 GPT2 GPT2 GPT2 GPT1 GPT1 Timer T6 External Up/Down Timer T5 External Up/Down Timer T6 Count Input Timer T5 Count Input Timer T4 External Up/Down Timer T2 External Up/Down Control Input Control Input
39 40 41 42 43 44
I I I I I I
Control Input Control Input
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II - PIN DATA (continued) Table 1 : Pin list (continued)
Symbol P2.0 - P2.7 P2.8 - P2.15 Pin 47 - 54 57 - 64 Type I/O Function 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins have alternate functions: P2.0 ... P2.7 P2.8 EX0IN ... P2.15 EX7IN T7IN CC0IO ... CC7IO CC8IO ... CC15IO CAPCOM: CC0 Capture Input/Compare Output ... CAPCOM: CC7 Capture Input/Compare Output CAPCOM: CC8 Capture Input/Compare Output Fast External Interrupt 0 Input ... CAPCOM: CC15 Capture Input/Compare Output Fast External Interrupt 7 Input CAPCOM2 Timer T7 Count Input
47 ... 54 57 ... 64
I/O ... I/O I/O I ... I/O I I I/O I/O I/O
P3.0 - P3.5 P3.6 - P3.13 P3.15
65 - 70 73 - 80 81
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins have alternate functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 T0IN T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST MTSR TxD0 RxD0 BHE WRH SCLK CLKOUT CAPCOM Timer T0 Count Input GPT2 Timer T6 Toggle Latch Output GPT2 Register CAPREL Capture Input GPT1 Timer T3 Toggle Latch Output GPT1 Timer T3 External Up/Down Control Input GPT1 Timer T4 Input for Count/Gate/Reload/Capture GPT1 Timer T3 Count/Gate Input GPT1 Timer T2 Input for Count/Gate/Reload/Capture SSC Master-Receive/Slave-Transmit I/O SSC Master-Transmit/Slave-Receive O/I ASC0 Clock/Data Output (Asynchronous/Synchronous) ASC0 Data Input (Asyn.) or I/O (Synchronous) External Memory High Byte Enable Signal, External Memory High Byte Write Strobe SSC Master Clock Output/Slave Clock Input System Clock Output (=CPU Clock)
65 66 67 68 69 70 73 74 75 76 77 78 79 80 81 P4.0 - P4.7 85 - 92
I O I O I I I I I/O I/O I/O O O I/O O I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits. Programming an I/O pin as input forces the corresponding output driver to high impedance state. For external bus configuration, Port 4 can be used to output the segment address lines: P4.0 - P4.4 P4.5 P4.6 P4.7 A16 - A20 A21 CAN_RxD A22 CAN_TxD A23 Least Significant Segment Address Line Segment Address Line CAN Receive Data Input Segment Address Line, CAN Transmit Data Output Most Significant Segment Address Line
85 - 89 90 91 92 RD 95
O O I O O O O
External Memory Read Strobe. RD is activated for every external instruction or data read access.
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ST10C167
II - PIN DATA (continued) Table 1 : Pin list (continued)
Symbol WR/WRL Pin 96 Type O Function External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. The active level is programmable. When the Ready function is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the ST10C167 to begin instruction execution out of external memory. A high level forces execution out of the internal Flash Memory. Port 0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, Port 0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width : 8-bit P0L.0 - P0L.7 : D0 - D7 P0H.0 - P0H.7 : I/O Multip lexed bus modes: Data Path Width : 8-bit P0L.0 - P0L.7 : AD0 - AD7 P0H.0 - P0H.7 : A8 - A15 P1L.0 - P1L.7 P1H.0 - P1H.7 118 - 125 128 - 135 I/O 16-bit D0 - D7 D8 - D15 16-bit AD0 - AD7 AD8 - AD15
READY/READY
97
I
ALE EA
98 99
O I
P0L.0 - P0L.7 P0H.0 P0H.1 - P0H.7
100 - 107 108 111 - 117
I/O
Port 1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 P1H.5 P1H.6 P1H.7 CC24IO CC25IO CC26IO CC27IO CAPCOM2: CAPCOM2: CAPCOM2: CAPCOM2: CC24 Capture CC25 Capture CC26 Capture CC27 Capture Input Input Input Input
132 133 134 135 XTAL1 XTAL2 138 137
I I I I I O
Input to the oscillator amplifier and input to the internal clock generator Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.
RSTIN
140
I
Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10C167. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence.
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II - PIN DATA (continued) Table 1 : Pin list (continued)
Symbol RSTOUT Pin 141 Type O Function Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog-timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10C167 to go into power down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Reference voltage for the A/D converter. Reference ground for the A/D converter. This pin is used as the timing pin for the return from powerdown circuit and power-up asynchronous reset. Digital Supply Voltage: = + 5V during normal operation and idle mode. > + 2.5V during power down mode Digital Ground.
NMI
142
I
VAREF VAGND RPD VDD
37 38 84 17, 46, 56, 72, 82, 93, 109, 126, 136, 144 18, 45, 55, 71, 83, 94, 110, 127, 139, 143
-
V SS
-
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ST10C167
III - FUNCTIONAL DESCRIPTION The architecture of the ST10C167 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The Figure 3 : Block diagram
16 32K Byte ROM for ST10C167 32 CPU-Core 16 Internal RAM
block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10C167.
16 PEC 2K Byte XRAM 16
Watchdog XTAL1 XTAL2
OSC.
Interrupt Controller CAN_RXD CAN_TXD
16
CAN
Port 4 Port 1 Port 0
GPT1
ASC usart
CAPCOM2
10-Bit ADC
PWM
16 16 8
External Bus Controller
CAPCOM1
SSC
GPT2
Port 2
16
BRG Port 3
BRG Port 7 Port 8
Port 6
Port 5
8
16
15
8
8
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ST10C167
IV - MEMORY ORGANIZATION The memory space of the ST10C167 is configured in a Von-Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Byte. The entire memory space can be accessed Bytewise or Wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. ROM : 32K Byte of on-chip ROM. RAM : 2K Byte of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. The register bank can consist of up to 16 wordwide (R0 to R15) and/or Bytewide (RL0, RH0, ..., RL7, RH7) general purpose registers. XRAM : 2K Byte of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is connected to the internal XBUS and is accessed like an external memory in 16-bit demultiplexed bus-mode without waitstate or read/write delay (80ns access at 25MHz CPU clock). Byte and Word access is allowed. The XRAM address range is 00'E000h 00'E7FFh if the XRAM is enabled (XPEN bit 2 of SYSCON register). As the XRAM appears like external memory, it cannot be used for the ST10C167's system stack or register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. If bit XRAMEN is cleared, then any access in the address range 00'E000h - 00'E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. SFR/ESFR : 1024 Byte (2 * 512 Byte) of address space is reserved for the special function register areas. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. CAN : Address range 00'EF00h - 00'EFFFh is reserved for the CAN Module access. The CAN is enabled by setting XPEN bit 2 of the SYSCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (Byte accesses are possible). Two wait states give an access time of 160ns at 25MHz CPU clock. No tristate waitstate is used. Note If the CAN module is used, Port 4 can not be programmed to output all 8 segment address lines. Thus, only 4 segment address lines can be used, reducing the external memory space to 5M Byte (1M Byte per CS line). In order to meet the needs of designs where more memory is required than is provided on chip, up to 16M Byte of external RAM and/or ROM can be connected to the microcontroller.
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V - CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10C167's instructions can be executed in one instruction cycle which requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bits to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16 bit multiplication in 5 cycles and a 32/16 bit division in 10 cycles.The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. Figure 4 : CPU Block Diagram
Internal RAM 2K Byte
The CPU uses an actual register context consisting of up to 16 Word wide GPRs physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 Byte is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.
CPU SP STKOV STKUN Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline 32 PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MLD Mul./Div.-HW Bit-Mask Gen.
R15
32K Byte on chip ROM
ALU 16-Bit Barrel-Shift CP ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr.
General Purpose Registers R0
Bank n
Bank i
16 16 Bank 0
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ST10C167
VI - EXTERNAL BUS CONTROLLER All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes: - 16-/18-/20-/24-bit addresses and 16-bit data, demultiplexed. - 16-/18-/20-/24-bit addresses and 16-bit data, multiplexed. - 16-/18-/20-/24-bit addresses and 8-bit data, multiplexed. - 16-/18-/20-/24-bit addresses and 8-bit data, demultiplexed. In demultiplexed bus modes addresses are output on Port1 and data is input/output on Port0 or P0L, respectively. In the multiplexed bus modes both addresses and data use Port0 for input/output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read/write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to 4 independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. A HOLD/HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1M Byte, 256K Byte or to 64K Byte. Port 4 outputs all 8 address lines if an address space of 16M Byte is used, otherwise four, two or no address lines. Chip select timing can be made programmable. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register.
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VII - INTERRUPT SYSTEM The interrupt response time for internal program execution is from 200ns to 480ns. The ST10C167 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The ST10C167 has 8 PEC channels each of Table 2 : Interrupt sources
Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT Vector Location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h Trap Number 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h
which offers such fast interrupt-driven data transfer capabilities. A interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 2 shows all the available ST10C167 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers :
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VII - INTERRUPT SYSTEM (continued) Table 2 : Interrupt sources (continued)
Source of Interrupt or PEC Service Request CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error PWM Channel 0...3 CAN Interface X-Peripheral Node X-Peripheral Node PLL Unlock Request Flag CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable Flag CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00E0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch Trap Number 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h
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VII - INTERRUPT SYSTEM (continued) Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 3 shows all of the possible exceptions or error conditions that can arise during run-time:
Table 3 : Exceptions or error conditions that can arise during run time
Exception Condit ion Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction Any [00'0000h- 00'01FCh] in steps of 4h Any [00h - 7Fh] Current CPU Priority UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h 0Ah 0Ah 0Ah 0Ah 0Ah I I I I I NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00'0008h 00'0010h 00'0018h 02h 04h 06h II II II RESET RESET RESET 00'0000h 00'0000h 00'0000h 00h 00h 00h III III III Trap Flag Trap Vector Vector Location Trap Number Trap Priority
[2Ch -3Ch]
[0Bh - 0Fh]
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VIII - CAPTURE/COMPARE (CAPCOM) UNIT The ST10C167 has two 16 channel CAPCOM units. They support generation and control of timing sequences on up to 32 channels with a maximum resolution of 320ns at 25MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/ underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare registers relative to external events. Each of the two capture/compare register arrays contain 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each register has one associated port pin which serves as an input pin Table 4 : Compare modes
Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode Function Interrupt-only compare mode ; several compare interrupts per timer period are possible Pin toggles on each compare match ; several compare events per timer period are possible Interrupt-only compare mode ; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow ; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match ; several compare events per timer period are possible.
for triggering the capture function, or as an output pin (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/ compare register, specific actions will be taken based on the selected compare mode (see Table 4). The input frequencies fTx for Tx are determined as a function of the CPU clocks. The formulas are detailed in the user manual. The timer input frequencies, resolution and periods which result from the selected pre-scaler option in TxI when using a 25MHz CPU clock are listed in the table below. The numbers for the timer periods are based on a reload value of 0000H. Note that some numbers may be rounded to 3 significant figures (see Table 5).
Table 5 : CAPCOM timer input frequencies, resolution and periods
Timer Input Selection TxI f CPU = 25MHz 000B Pre-scaler for fCPU Input Frequency Resolution Period 8 3.125MHz 320ns 21.0ms 001B 16 1.56MHz 640ns 41.9ms 010B 32 781KHz 1.28s 83.9ms 011B 64 391KHz 2.56s 167ms 100 B 128 195KHz 5.12s 336ms 101B 256 97.7KHz 10.24s 671ms 110B 512 48.8KHz 20.48s 1.34s 111B 1024 24.4KHz 40.96s 2.68s 17/65
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IX - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. IX.1 - GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which is the gate or the clock input. The table below lists the timer input frequencies, resolution and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode (see Table 6). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution measurement of long time periods. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.
Table 6 : GPT1 timer input frequencies, resolution and periods
Timer Input Selection T2I / T3I / T4I
fCPU = 25MHz
000B Pre-scaler factor Input Frequency Resolution Period 8 001B 16 010B 32 781.3KHz 1.28s 83.9ms 011B 64 390.6KHz 2.56s 167ms 100B 128 195.3KHz 5.12s 336ms 101 B 256 97.66KHz 10.24s 671ms 110B 512 48.83KHz 20.48s 1.34s 111B 1024 24.41KHz 40.96s 2.68s
3.125MHz 1.563MHz 320ns 21.0ms 640ns 41.9ms
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IX - GENERAL PURPOSE TIMER UNIT (continued) Figure 5 : Block diagram of GPT1
T2EUD
U/D GPT1 Timer T2 2n n=3...10 Interrupt Request
CPU Clock T2IN
T2 Mode Control
Reload Capture
CPU Clock
2n n=3...10
T3IN
T3 Mode Control
T3OUT GPT1 Timer T3 U/D T3OTL
T3EUD
T4IN CPU Clock
T4 Mode Control 2n n=3...10
Capture Reload
Interrupt Request Interrupt Request
GPT1 Timer T4 U/D
T4EUD
IX.2 - GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3 inputs T3IN and/or T3EUD. This is advantageous when T3 operates in Incremental Interface Mode. Table 7 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode.
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IX - GENERAL PURPOSE TIMER UNIT (continued) Table 7 : GPT2 timer input frequencies, resolution and periods
Timer Input Selection T5I / T6I fCPU = 25MHz 000B Pre-scaler factor Input Frequency Resolution Period 4 6.25MHz 160ns 10.49ms 001B 8 3.125MHz 320ns 21.0ms 010B 16 1.563MHz 640ns 41.9ms 011B 32 781.3KHz 1.28s 83.9ms 100B 64 390.6KHz 2.56s 167ms 101B 128 195.3KHz 5.12s 336ms 110B 256 97.66KHz 10.24s 671ms 111B 512 48.83KHz 20.48s 1.34s
Figure 6 : Block diagram of GPT2
T5EUD
U/D
CPU Clock T5IN
2n n=2...9
T5 Mode Control
GPT2 Timer T5 Clear Capture
Interrupt Request
CAPIN GPT2 CAPREL
Interrupt Request
Reload
Interrupt Request
T6IN CPU Clock
Toggle FF 2n n=2...9
T6 Mode Control
GPT2 Timer T6 U/D
T60TL
T6OUT to CAPCOM Timers
T6EUD
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X - PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. Table 8 shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests.
Table 8 : PWM unit frequencies and resolution at 25MHz clock
Mode 0 CPU Clock/1 CPU Clock/64 Mode 1 CPU Clock/1 CPU Clock/64 Resoluti on 40ns 2.56ns Resoluti on 40ns 2.56ns 8-bit 97.66KHz 1.526KHz 8-bit 48.82KHz 762.9Hz 10-bit 24.41KHz 381.5Hz 10-bit 12.20KHz 190.7 Hz 12-bit 6.104KHz 95.37Hz 12-bit 3.05KHz 47.68Hz 14-bit 1.526KHz 23.84Hz 14-bit 762.9Hz 11.92Hz 16-bit 0.381KHz 5.96Hz 16-bit 190.7Hz 2.98Hz
Figure 7 : Block diagram of PWM module
PPx Period Register * Match
Comparator
Clock 1 Clock 2
Input Control
Run
* PTx 16-Bit Up/Down Counter
Up/Down/ Clear Control
Comparator
Match
Output Control Enable
POUTx
Shadow Register
Write Control
* User read-& writeable
PWx Pulse Width Register *
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XI - PARALLEL PORTS The ST10C167 provides up to 111 I/O lines organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as input or output via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL-or CMOS-like), where the special CMOS-like input threshold reduces noise sensitivity due to the input hysteresis. The input thresholds are selected with bit of PICON register dedicated to blocks of 8 input pins (2-bit for port2, 2-bit for port3, 1-bit for port7, 1-bit for port8). All pins of I/O ports also support an alternate programmable function: - Port0 and Port1 may be used as address and data lines when accessing external memory. - Port 2, Port 7 and Port 8 are associated with the capture inputs or with the compare outputs of the CAPCOM units and/or with the outputs of the PWM module. - Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). - Port 4 outputs the additional segment address bits A16 to A23 in systems where segmentation is enabled to access more than 64K Byte of memory.
- Port 5 is used as analog input channels of the A/D converter or as timer control signals.
- Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. All port lines that are not used for alternate functions may be used as general purpose I/O lines.
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XII - A/D CONVERTER
A10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. Overrun error detection/protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The AD converter of the ST10F168 supports different conversion modes : - Single channel single conversion : the analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. - Single channel continuous conversion : the analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. - Auto scan single conversion : the analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register. The data can be transfered to the RAM by interrupt software management or using the powerfull Peripheral Event Controller data transfert. - Auto scan continuous conversion : the analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. The data can be transfered to the RAM by interrupt software management or using the powerfull Peripheral Event Controller data transfert. - Wait for ADDAT read mode : when using continuous modes, in order to avoid to overwrite the result of the current conversion by the next one, the ADWR bit of ADCON control register
must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold. - Channel injection mode : when using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10 bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed.
The Table : 9 ADC sample clock and conversion time shows the ADC unit conversion clock, sample clock.
A complete conversion will take 14tCC + 2 tSC + 4 TCL. This time includes the conversion it-self, the sampling time and the time required to transfer the digital value to the result register. For example, at 25MHz of CPU clock, minimum complete conversion time is 7.76s. The A/D converter provides automatic offset and linearity self calibration. The calibration operation is performed in two ways: - A full calibration sequence is performed after a reset and lasts 1.6ms minimum (at 25MHz CPU clock). During this time, the ADBSY flag is set to indicate the operation. Normal conversion can be performed during this time. The duration of the calibration sequence is then extended by the time consumed by the conversions. Note : After a power-on reset, the total unadjusted error (TUE) of the ADC might be worse than 2LSB (max. 4LSB). During the full calibration sequence, the TUE is constantly improved until at the end of the cycle, TUE is within the specified limits of 2LSB. - One calibration cycle is performed after each conversion : each calibration cycle takes 4 ADC clock cycles. These operation cycles ensure constant updating of the ADC accuracy, compensating changing operating conditions.
Sample Clock tSC ADSTC 00 01 10 11 tCC tCC x 2 tCC x 4 tCC x 8 At fCPU = 25MHz 0.48s2 0.96s2 1.92s2 3.84s2
Table 9 : ADC sample clock and conversion time
Conversion Clock tCC ADCTC 00 01 10 11
Note 1. See chapter XX. 2. tCC = TCL x 24.
TCL1 = 1/2 x fXTAL TCL x 24 Reserved, do not use TCL x 96 TCL x 48
At fCPU = 25MHz 0.48s 1.92s 0.96s
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XIII - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous/synchronous serial channel (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, 3 separate interrupt vectors are provided for each serial channel. ASCO ASCO supports full-duplex asynchronous communication up to 781.25K Baud and half-duplex synchronous communication up to 5M Baud at 25MHz system clock. For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. The table below lists various commonly used Baud rates together with the required reload values and the deviation errors compared to the intended Baud rate (see Table 10). For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate.
Table 10 : Commonly used Baud rates by reload value and deviation errors
S0BRS = `0', fCPU = 25MHz Baud Rate (Baud) 781250 56000 38400 19200 9600 4800 2400 1200 600 95 Deviation Error 0.0% +7.3% / -0.4% +1.7% / -3.1% +1.7% / -0.8% +0.5% / -0.8% +0.5% / -0.1% +0.2% / -0.1% +0.0% / -0.1% +0.0% / -0.1% +0.4% / 0.4% Reload Value 0000H 000C H / 000DH 0013H / 0014H 0027H / 0028H 0050H/ 0051H 00A1 H / 00A2H 0144H / 0145H 028A H / 028BH 0515H / 0516H 1FFFH / 1FFFH S0BRS = `1', fCPU = 25MHz Baud Rate (Baud) 520833 56000 38400 19200 9600 4800 2400 1200 600 75 63
Note
Deviation Error 0.0% +3.3% / -7.0% +4.3% / -3.1% +0.5% / -3.1% +0.5% / -1.4% +0.5% / -0.5% +0.0% / -0.5% +0.0% / -0.2% +0.0% / -0.1% +0.0% / 0.0% +0.9% / 0.9%
Reload Value 0000 H 0008H / 0009H 000CH / 000DH 001AH / 001BH 0035H / 0036H 006BH / 006CH 00D8H / 00D9H 01B1H / 01B2H 0363H / 0364H 1B1FH / 1B20H 1FFFH / 1FFFH
The deviation errors given in the table above are rounded. Using a Baud rate crystal will provide correct Baud rates without deviation errors.
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XIII - SERIAL CHANNELS (continued) High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communication between the ST10C167 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows Table 11 : Synchronous Baud rate and reload values
Baud Rate Reserved use a reload value > 0. 5M Baud 3.3M Baud 2.5M Baud 2M Baud 1M Baud 100K Baud 10K Baud 1K Baud 190.7 Baud Bit Time --200ns 303ns 400ns 500ns 1s 10s 100s 1ms 5.2ms Reload Value 0000 H 0001 H 0002 H 0004 H 0005 H 000BH 007C H 04E1H 30D3 H FFFFH
communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSC with a separate serial clock signal. The serial channel SSC has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation independent from the timers. SSCBR is the dual-function Baud Rate Generator/ Reload register. Table 11 lists some possible Baud rates against the required reload values and the resulting bit times for a 25MHz CPU clock.
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XIV - CAN MODULE The integrated CAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active) i.e. the on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN module provides full CAN functionality on up to 15 message objects. Message object 15 can be configured for basic CAN functionality. Both modes provide separate masks for acceptance filtering, allowing a number of identifiers in full CAN mode to be accepted and disregarding a number of identifiers in basic CAN mode. All message objects can be updated independent from other objects and are equipped for the maximum message length of 8 Byte. The bit timing is derived from the XCLK and is programmable up to a data rate of 1M Baud. The CAN module uses two pins to interface to a bus transceiver. XV - WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high Byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced
Table 12 : Watchdog time range for 25MHz CPU clock
Prescaler for fCPU Reload value in WDTREL 2 (WDTIN = `0') FF H 00H 20.48s 5.24ms 128 (WDTIN = `1') 1.31ms 336ms
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ST10C167
XVI - INSTRUCTION SET SUMMARY The table below lists the instructions of the ST10C167. The various addressing modes, instruction operation, parameters for conditional Table 13 : Instruction set summary
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC Add Word (Byte) operands Add Word (Byte) operands with Carry Subtract Word (Byte) operands Subtract Word (Byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide register MD by direct GPR (32-/16-bit) Complement direct Word (Byte) GPR Negate direct Word (Byte) GPR Bitwise AND, (Word/Byte operands) Bitwise OR, (Word/Byte operands) Bitwise XOR, (Word/Byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct Word memory with immediate data Compare Word (Byte) operands Compare Word data to GPR and decrement GPR by 1/2 Compare Word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct Word GPR and store result in direct Word GPR Shift left/right direct Word GPR Rotate left/right direct Word GPR Arithmetic (sign bit) shift right direct Word GPR Move Word (Byte) data Move Byte operand to Word operand with sign extension Move Byte operand to Word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Description Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4 2/4 2/4 4 4 4 4 27/65
execution of instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Family Programming Manual".
ST10C167
XVI - INSTRUCTION SET SUMMARY (continued) Table 13 : Instruction set summary (continued)
Mnemonic JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct Word register onto system stack & call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct Word register onto/from system stack Push direct Word register onto system stack and update register with Word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct Word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (assumes NMI-pin low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
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ST10C167
XVII - SYSTEM RESET The internal system reset function is invoked either by asserting a hardware reset signal on pin RSTIN (Hardware Reset Input), by the execution of the SRST instruction (Software Reset) or by an overflow of the watchdog timer. Whenever one of these conditions occurs, the microcontroller is reset into its predefined default state. The following type of reset are implemented on the ST10C167: active at that time the internal reset condition is prolonged until RSTIN becomes inactive.
Asynchronous hardware reset Asynchronous reset does not require a stabilized clock signal on XTAL1, as it is not internally resynchronized. It immediately resets the microcontroller into its default reset state. This asynchronous reset is required upon power-up of the chip and may be used during catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before exiting the reset condition. Therefore, only the entry of this hardware reset is asynchronous. Synchronous hardware reset (warm reset) A warm synchronous hardware reset is triggered when the reset input signal RSTIN is latched low and RPD (Pin 84) is high. The I/Os are immediately (asynchronously) set in high impedance, RSTOUT is driven low. After negation of RSTIN is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. Then, the internal reset sequence starts for 1024 TCL (512 CPU clock cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 5 in SYSCON register), RSTIN pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state. Note that after all reset sequences, bit BDRSTEN is cleared. After the reset sequence has been completed, the RSTIN input is sampled. If the reset input signal is
Software reset The reset sequence can be triggered at any time by the protected instruction SRST (software reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. As for a synchronous hardware reset, the reset sequence lasts 1024 TCL (512 CPU clock cycles), and drives the RSTIN pin low. Watchdog timer reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after the programmed waitstates. When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. The internal reset sequence is then started. The watchdog reset cannot occur while the ST10C167 is in bootstrap loader mode. Bidirectional reset This feature is enabled by bit 3 of the SYSCON register. The bidirectional reset makes the watchdog timer reset and software reset externally visible. It is active for the duration of an internal reset sequences caused by a watchdog timer reset and software reset. This means that the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL. The consequence is that during a watchdog timer reset or software reset, the behavior of the ST10C167 is equal to an external hardware reset.
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ST10C167
XVIII - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can be configured by software in order to be terminated only by a hardware reset or by an external interrupt source on fast external interrupt pins. There are two different operating Power Down modes: - Protected power down mode: selected by setting bit PWDCFG in the SYSCON register to `0'. This mode can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent. The microcontroller enters the NMI trap routine and saves the internal state into RAM. The trap routine then sets a flag or writes a bit pattern into specific RAM locations, and executes the PWRDN instruction. If the NMI pin is still low at this time, Power Down mode will be entered, if not program execution continues. During power down the voltage at the VCC pins can be lowered to 2.5 V and the contents of the internal RAM will still be preserved. - Interruptible power down mode: this mode is selected by setting bit PWDCFG in the SYSCON register. The CPU and peripheral clocks are frozen, and the oscillator and PLL are stopped. To exit power down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40ns. This signal enables the internal oscillator and PLL circuitry, and turns on the weak pull-down. If the Interrupt was enabled before entering power down mode, the device executes the interrupt service routine, and then resumes execution after the PWRDN instruction. If the interrupt was disabled, the device executes the instruction following PWRDN instruction, and the Interrupt Request Flag remains set until it is cleared by software. All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated during the last bus access.
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XIX - SPECIAL FUNCTION REGISTER OVERVIEW Table 14 lists all SFRs which are implemented in the ST10C167 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Table 14 : Special function registers listed by name
Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC b b b Physical address FF98h FFA0h FEA0h F0A0h FE18h FE1Ah FE1Ch FE1Eh FF9Ah FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah b FF88h FE80h b FF78h FE82h b FF7Ah FE84h b FF7Ch FE86h b FF7Eh FE88h b FF80h FE8Ah b FF82h FE8Ch b FF84h FE8Eh b FF86h FE90h E 8-bit address CCh D0h 50h 50h 0Ch 0Dh 0Eh 0Fh CDh 86h 8Ah 8Bh 8Ch 8Dh 25h C4h 40h BCh 41h BDh 42h BEh 43h BFh 44h C0h 45h C1h 46h C2h 47h C3h 48h Description Reset value
An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
A/D Converter End Of Conversion Interrupt Control Register 0000h A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register EX0IN Interrupt Control Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
BUSCON0 b BUSCON1 b BUSCON2 b BUSCON3 b BUSCON4 b CAPREL CC8IC CC0 CC0IC CC1 CC1IC CC2 CC2IC CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8
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XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued)
Name CC8IC CC9 CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 32/65 b b b b b b b b b b b b b b b b b b b Physical address FF88h FE92h FF8Ah FE94h FF8Ch FE96h FF8Eh FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FE60h F160h FE62h F162h FE64h F164h FE66h F166h FE68h F168h FE6Ah F16Ah FE6Ch F16Ch FE6Eh F16Eh FE70h F170h FE72h F172h FE74h F174h FE76h E E E E E E E E E E E 8-bit address C4h 49h C5h 4Ah C6h 4Bh C7h 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h B0h 31h B1h 32h B2h 33h B3h 34h B4h 35h B5h 36h B6h 37h B7h 38h B8h 39h B9h 3Ah BAh 3Bh Description CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Register CAPCOM Register 17 CAPCOM Register 17 Interrupt Control Register CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Register CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Register CAPCOM Register 20 CAPCOM Register 20 Interrupt Control Register CAPCOM Register 21 CAPCOM Register 21 Interrupt Control Register CAPCOM Register 22 CAPCOM Register 22 Interrupt Control Register CAPCOM Register 23 CAPCOM Register 23 Interrupt Control Register CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
ST10C167
XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued)
Name CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CP CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DP7 DP8 DPP0 DPP1 DPP2 DPP3 EXICON IDCHIP IDMANUF IDMEM b b b b b b b b b b b b b b b b b b b b b b b b b Physical address F176h FE78h F178h FE7Ah F184h FE7Ch F18Ch FE7Eh F194h FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h FE10h FF6Ah FE08h F100h F102h F104h F106h FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h F1C0h F07Ch F07Eh F07Ah E E E E E E E E E E E E E 8-bit address BBh 3Ch BCh 3Dh C2h 3Eh C6h 3Fh CAh A9h AAh ABh ACh 91h 92h 93h 94h 08h B5h 04h 80h 81h 82h 83h E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h E0h 3Eh 3Fh 3Dh Description CAPCOM Register 27 Interrupt Control Register CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Register CAPCOM Register 29 CAPCOM Register 29 Interrupt Control Register CAPCOM Register 30 CAPCOM Register 30 Interrupt Control Register CAPCOM Register 31 CAPCOM Register 31 Interrupt Control Register CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0h Direction Control Register P1L Direction Control Register P1h Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10 bit) CPU Data Page Pointer 1 Register (10 bit) CPU Data Page Pointer 2 Register (10 bit) CPU Data Page Pointer 3 Register (10 bit) External Interrupt Control Register Device Identifier Register Manufacturer Identifier Register On-chip Memory Identifier Register Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 00h 00h 00h 00h 0000h 0001h 0002h 0003h 0000h 0A7h1 0020h1 3020h1 33/65
ST10C167
XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued)
Name IDPROG MDC MDH MDL ODP2 ODP3 ODP6 ODP7 ODP8 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 P7 P8 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 PP3 PSW PT0 PT1 b b b b b b b b b b b b b b b b b b Physical address F078h FF0Eh FE0Ch FE0Eh F1C2h F1C6h F1CEh F1D2h F1D6h FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FFD0h FFD4h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh F1C4h F038h F03Ah F03Ch F03Eh FF10h F030h F032h E E E E E E E E E E E E E 8-bit address 3Ch 87h 06h 07h E1h E3h E7h E9h EBh 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h E8h EAh 60h 61h 62h 63h 64h 65h 66h 67h E2h 1Ch 1Dh 1Eh 1Fh 88h 18h 19h Description Programming Voltage Identifier Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of Port0) Port 0 High Register (Upper half of Port0) Port 1 Low Register (Lower half of Port1) Port 1 High Register (Upper half of Port1) Port 2 Register Port 3 Register Port 4 Register (8 bit) Port 5 Register (read only) Port 6 Register (8 bit) Port 7 Register (8 bit) Port 8 Register (8 bit) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register PWM Module Period Register 0 PWM Module Period Register 1 PWM Module Period Register 2 PWM Module Period Register 3 CPU Program Status Word PWM Module Up/Down Counter 0 PWM Module Up/Down Counter 1 Reset value 9A40h1 0000h 0000h 0000h 0000h 0000h 00h 00h 00h FFFFh 00h 00h 00h 00h 0000h 0000h 00h XXXXh 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10C167
XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued)
Name PT2 PT3 PW0 PW1 PW2 PW3 PWMCON0b PWMCON1b PWMIC RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON T0 T01CON T0IC T0REL T1 T1IC T1REL T2 b b b b b b b b b b b b b b b Physical address F034h F036h FE30h FE32h FE34h FE36h FF30h FF32h F17Eh F108h FEB4h FFB0h FF70h FEB2h FF6Eh F19Ch FEB0h FF6Ch FE12h F0B4h FFB2h FF76h F0B2h FF74h F0B0h FF72h FE14h FE16h FF12h FE50h FF50h FF9Ch FE54h FE52h FF9Eh FE56h FE40h E E E E E E E E 8-bit address 1Ah 1Bh 18h 19h 1Ah 1Bh 98h 99h BFh 84h 5Ah D8h B8h 59h B7h CEh 58h B6h 09h 5Ah D9h BBh 59h BAh 58h B9h 0Ah 0Bh 89h 28h A8h CEh 2Ah 29h CFh 2Bh 20h Description PWM Module Up/Down Counter 2 PWM Module Up/Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 PWM Module Interrupt Control Register System Start-up Configuration Register (read only) Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baud rate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h XXh 0000h 0000h 0000h XXh 0000h 0000h 00h 0000h FC00h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h FA00h FC00h 0xx0h2 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued)
Name T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS b b b b b b b b b b b b b b b b b b b Physical address FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h F050h FF20h F17Ah F054h F052h F17Ch F056h FFACh FEAEh FFAEh F186h F18Eh F196h F19Eh FF1Ch E E E E E E E E E E 8-bit address A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h 28h 90h BEh 2Ah 29h BFh 2Bh D6h 57h D7h C3h C7h CBh CFh 8Eh Description GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register CAPCOM Timer 8 Reload Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register CAN Module Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL Unlock Interrupt Control Register Constant Value 0's Register (read only) Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 000xh3 0000h4 0000h4 0000h4 0000h4 0000h
Notes 1. The value depends on the silicon revision and is described in the chapter XIX.1. 2. The system configuration is selected during reset. 3. Bit WDTR indicates a watchdog timer triggered reset. 4. The XPnIC Interrupt Control Registers control the interrupt requests from integrated X-Bus peripherals. Nodes where no X-Peripherals are connected may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
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XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) XIX.1 - Identification Registers The ST10C167 has four Identification registers, mapped in ESFR space. These registers contain: - - - - a manufacturer identifier, a chip identifier, with its revision, a internal memory and size identifier, programming voltage description. ESFR IDCHIP (F07Ch / 3Eh) ESFR
Description
IDCHIP: Device Identifier - 0A72h for ST10C167. IDMEM (F07Ah / 3Dh) ESFR
Description
IDMEM: 1008h for ST10C167 (MCU with ROM). IDPROG (F078h / 3Ch) ESFR
IDMANUF (F07Eh / 3Fh)
Description IDMANUF : Manufacturer Identifier - 0400h: STmicroelectronics Manufacturer (JTAG worldwide normalisation).
Description
IDPROG: 0000h for ST10C167 (MCU with ROM).
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XX - ELECTRICAL CHARACTERISTICS XX.1 - Absolute maximum ratings
Symbol VSS VSS Parameter Voltage on V DD pins with respect to ground Voltage on any pin with respect to ground Input current on any pin during overload condition Absolute sum of all input currents during overload condition Ptot Tamb Tstg Power Dissipation Ambient Temperature under bias Storage Temperature Value -0.5, +6.5 -0.3 to VDD +0.3 -10, +10 |100| 1.5 -40, +125 -65, +150 Unit V V mA mA W C C
Note
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VINST10C167, the symbol "SR" for System Requirement is included in the "Symbol" column.
XX.2 - Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10C167 and its demands on the system. Where the ST10C167 logic provides signals with their respective timing characteristics, the symbol "CC"
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XX - ELECTRICAL CHARACTERISTICS (continued) XX.3 - DC characteristics VDD = 5V 10%, VSS = 0V, fCPU = 25MHz, Reset active, TA = -40 to +125C, unless otherwise specified. Table 15 : DC characteristics
Symbol V IL VILS V IH V IH1 V IH2 VIHS HYS VOL VOL1 VOH VOH1 IOZ1 IOZ2 IOV RRST IRWH
2
Parameter Input low voltage Input low voltage (special threshold) Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage (Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage 1 (all other outputs) Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pull-up resistor
5 4
Test Condition s - - - - - - - IOL = 2.4 mA IOL1 = 1.6 mA IOH = - 500 A IOH = -2.4 mA IOH = - 250 A IOH = - 1.6 mA 0 V < VIN < VDD 0 V < VIN < VDD
58
Mininmum - 0.5 - 0.5 0.2 VDD + 0.9 0.6 VDD 0.7 VDD 0.8 VDD - 0.2 400 - - 0.9 VDD 2.4 0.9 VDD 2.4 - - - 50 - -500 40 - - -500 - -100 - - 20 + 6 * fCPU -
Maximum 0.2 VDD - 0.1 2.0 VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD+ 0.5 0.45 0.45 - - 0.5 1 5 250 -40 - - 500 -40 - -10 - 20 10 20 + 7 * fCPU 20 + 3 * fCPU 400
Unit V V V V V V mV V V V V V A A mA k A A A A A A A A A pF mA
SR SR SR SR SR SR CC CC CC CC CC CC SR CC
- VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax
Read/Write inactive current Read/Write active current 4 ALE inactive current 4 ALE active current 4 Port 6 inactive current 4 Port 6 active current 4
IRWL 3 IALEL 2 IALEH 3 IP6H 2 I P6L 3 IP0H 2 I P0L 3 IIL C IO ICC IID IPD CC CC
Port0 configuration current 4
XTAL1 input current Pin capacitance 5 (digital inputs/outputs) Power supply current
0 V < VIN < VDD f = 1 MHz TA = 25 C RSTIN = VIH1 fCPU in [MHz] 6 RSTIN = VIH1 fCPU in [MHz] 6 VDD = 5.5 V 7
Idle mode supply current
mA A
Power-down mode supply current
100
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XX - ELECTRICAL CHARACTERISTICS (continued)
Notes 1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2. The maximum current may be drawn while the respective signal line remains inactive. 3. The minimum current must be drawn in order to drive the respective signal line active. 4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected if they are used as CSx output and the open drain function is not enabled. 5. Partially tested, guaranteed by design characterization. 6. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 7. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0V to 0.1V or at VDD - 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected. 8. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < VSS-0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA (see Figure 8).
Figure 8 : Supply/idle current as a function of operating frequency
I [mA] 195
ICCmax ICCtyp
95
IIDmax IIDtyp
10 5 10 15 20 25 fCPU [MHz]
XX.3.1 - A/D converter characteristics VDD = 5V 10%, VSS = 0V, TA = -40 to +125C 4.0V VAREF VDD + 0.1V, VSS - 0.1V VAGND VSS + 0.2V (see Table 16) Table 16 : A/D converter characteristics
Symbol VAIN tS tC TUE R AREF R ASRC C AIN 40/65 Parameter Test Condition s
1 24 34
Min. VAGND - - - - - -
Max. VAREF 2 tSC 14 tCC + tS + 4TCL 2 tCC /165 - 0.25 tS / 330 - 0.25 33
Unit V
SR Analog input voltage range CC Sample time CC Conversion time CC Total unadjusted error SR Internal source resistance of reference
5 67 voltage t CC in [ns]
LSB k k pF
SR Internal resistance of analog source CC ADC input capacitance
tS in [ns] 2 7
7
ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued)
Notes 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000 H or X3FFH, respectively. 2. During the sample time the input capacitance C I can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversionresult. Values for the sample clock t SC depend on programming and can be taken from the table above. 3. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above. 4. This parameter is fixed by ADC control logic. 5. TUE is tested at VAREF = 5.0V, VAGND = 0V, VCC = 4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum of 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA. During the reset calibration sequence the maximum TUE may be 4 LSB. 6. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. 7. Partially tested, guaranteed by design characterization.
Sample time and conversion time of the ST10C167's ADC are programmable. The table below should be used to calculate the above timings.
ADCON.15|14 (ADCTC) 00 01 10 11 Conversion clock tCC TCL * 24 Reserved, do not use TCL * 96 TCL * 48 ADCON.13|12 (ADSTC) 00 01 10 11 Sample clock tSC t CC tCC * 2 tCC * 4 tCC * 8
XX.4 - AC characteristics Test waveforms Figure 9 : Input output waveforms
2.4V 0.2V DD+0.9 0.2VDD+0.9
Test Points
0.45V
0.2V DD-0.1
0.2V DD-0.1
AC inputs during testing are driven at 2.4V for a logic `1' and 0.4V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
Figure 10 : Float waveforms
V OH VOH -0.1V Timing Reference Points V OL +0.1V VOL For timing purposes a port pin is no longer floating when VLOAD changes of 100mV. It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA). 41/65
V Load +0.1V V Load VLoad -0.1V
ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.1 - Definition of internal timing The internal operation of the ST10C167 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" periods (see Figure 11). The CPU clock signal can be generated by different mechanisms. The duration of TCL periods and their variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10C167. The example for PLL operation shown in Figure 11 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). XX.4.2 - Clock generation modes Table 18 shows the association of the combinations of these three bits with the respective clock generation mode.
Figure 11 : Generation mechanisms for the CPU clock
Phase locked loop operation fXTAL fCPU
TCL TCL
Direct Clock Drive fXTAL fCPU
TCL TCL
Prescaler Operation fXTAL fCPU
TCL TCL
Table 17 : CPU Frequency Generation
P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CPU Frequency fCPU = fXTAL x F FXTAL x 4 FXTAL x 3 FXTAL x 2 FXTAL x 5 FXTAL x 1 FXTAL x 1.5 FXTAL / 2 FXTAL x 2.5 External Clock Input Range 1 2.5 to 6.25MHz 3.33 to 8.33MHz 5 to 12.5MHz 2 to 5MHz 1 to 25MHz 6.66 to 16.6MHz 2 to 50MHz 4 to 10MHz CPU clock via prescaler Direct drive 2 Notes Default configuration
Notes 1. The external clock input range refers to a CPU clock range of 10...25MHz. 2. The maximum frequency depends on the duty cycle of the external clock signal.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.3 - Prescaler operation When pins P0.15-13 (P0H.7-5) equal '001' during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCLs, therefore, can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL is running on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. XX.4.4 - Direct drive When pins P0.15-13 (P0H.7-5) equal '011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated by the following formula:
T CLmi n = 1 f X T A L*DC mi n DC = duty cycle
XX.4.5 - Oscillator watchdog (OWD) When the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows : After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, the bit OWDDIS (bit 4 of SYSCON register) must be set. When the OWD is enabled, the PLL is running on its free-running frequency, and increment the Oscillator Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. XX.4.6 - Phase locked loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances.
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
2TC L = 1 f X TAL
Note The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCL min. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL is running on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes FCPU to keep it locked on FXTAL. The relative deviation of TCL is the maximum when it is refered to one TCL period. It decreases according to the formula and to the Figure 12 given below. For N periods of TCL the minimum value is computed using the corresponding deviation DN:
TCL D N x 1 - ------------ MIN NO M 100 D = ( 4 - N 15 ) [ % ] N = T CL
where N = number of consecutive TCL periods and 1 N 40. So for a duration of 3 TCL periods (N = 3): D3 = 4 - 3/15 = 3.8% 3TCLmin = 3TCLNOM x (1 - 3.8/100) = 3TCLNOM x 0.962 3TCLmin = (57.72ns at fCPU = 25MHz) This is especially important for bus cycles using wait states and for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is negligible.
Figure 12 : Approximated maximum PLL jitter Max.jitter [%] 4 3 2 1 2 4 8 16 32 N This approximated formula is valid for 1 N 40 and 10MHz fCPU 25MHz.
XX.4.7 - Memory cycle variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes how these variables are to be computed.
Symbol tA tC tF ALE Extension Memory Cycle Time wait states Memory Tristate Time Description Values TCL * 2TCL * (15 - ) 2TCL * (1 - )
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.8 - External clock drive XTAL1 VDD = 5V 10%, VSS = 0V, TA = -40 to +125C unless otherwise specified.
fCPU = fXTAL Symbol Parameter Min. tOSC t1 t2 t3 t4 SR SR SR SR SR Oscillator period High time Low time Rise time Fall time 40 1 18 3 18 3 - - Max. 1000 - - 10 3 10 3 Min. 20 2 63 63 - - Max. 500 - - 63 63 f CPU = fXTAL / 2 fCPU = fXTAL * N N = 1.5/2,/2.5/3/4/5 Min. 40 * N 10 3 10 3 - - Max. 100 * N - - 10 3 10 3 ns ns ns ns ns Unit
Notes 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. 25MHz is the maximum input frequency when using an external crystal oscillator; however, 50MHz can be applied with an external clock source. 3. The input clock signal must reach the defined levels VIL and VIH2.
Figure 13 : External clock drive XTAL1
t1 t3 t4
VIH2 t2
VIL
tOSC XX.4.9 - Multiplexed bus VDD = 5V 10%, VSS = 0V, TA = -40 to +125C CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF, CL (for Port 6, CS) = 100pF ALE cycle time = 6 TCL + 2tA + tC + tF (120ns at 25MHz CPU clock without wait states) Table 18 : Multiplexed bus characteristics
Max. CPU Clock = 25MHz Min. t5 t6 t7 t8 t9 CC CC CC CC CC ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) 10 + tA 4 + tA 10 + tA 10 + tA -10 + tA Max. - - - - - Variable CPU Clock 1/2TCL = 1 to 25MHz Min. TCL - 10 + tA TCL - 16+ tA TCL - 10 + tA TCL - 10 + tA -10 + tA Max. - - - - - ns ns ns ns ns
Symbol
Parameter
Unit
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Table 18 : Multiplexed bus characteristics (continued)
Max. CPU Clock = 25MHz Min. t101 t111 t12 t13 t14 t15 t16 t17 t18 t191 t22 t23 t25 t27 t38 t39 t40 t42 t43 t441 t451 t46 t47 CC CC CC CC SR SR SR SR SR SR CC CC CC CC CC SR CC CC CC CC CC SR SR Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address/Unlatched data in CS to valid - - 30 + tC 50 + tC - - - - 0 - 20 + tC 26 + tF 26 + tF 26 + tF -4 - t A - 46 + tF 16 + tA -4 + tA - - - - Max. 6 26 - - 20 + tC 40 + tC 40 + tA + t C 50 + 2tA + tC - 26 + tF - - - - 10 - tA 40 + t C + 2tA - - - 0 20 16 + tC 36 + tC Variable CPU Clock 1/2TCL = 1 to 25MHz Min. - - 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - 2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF -4 - tA - 3TCL - 14 + tF TCL - 4 + tA -4 + t A - - - - Max. 6 TCL + 6 - - 2TCL - 20+ tC 3TCL - 20+ tC 3TCL - 20 + t A + tC 4TCL - 30 + 2tA + t C - 2TCL - 14 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 24 + tC 3TCL - 24 + tC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR ALE falling edge to Latched CS Latched CS low to valid data in Latched CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay)
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Table 18 : Multiplexed bus characteristics (continued)
Max. CPU Clock = 25MHz Min. t48 t49 t50 t51 t521 t54 t56
Note
Symbol
Parameter
Variable CPU Clock 1/2TCL = 1 to 25MHz Min. 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14+ tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF Max. - - - - 2TCL - 20 + tF - -
Unit
Max. - - - - 20 + tF - -
CC CC CC SR SR CC CC
RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
30 + tC 50 + tC 26 + tC 0 - 20 + tF 20 + tF
ns ns ns ns ns ns ns
1. Guaranteed by design characterization.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 14 : External Memory Cycle : multiplexed bus, with/without read/write delay, normal ALE
CLKOUT
t5
ALE
t16
t25
t6
t38
t17
t40 t39 t27
CSx
t6
A23-A16
(A15-A8) BHE
t17
Address
t27
t16
Read Cycle BUS (P0)
t6m
Address
t7
t18
Data In Address
t8
RD
t10 t14 t12
t19
t13 t9
Write Cycle BUS (P0)
t11 t15 t23
Data Out
Address
t8
WR WRL WRH
t22 t12 t13
t9
48/65
ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 15 : External Memory Cycle: multiplexed bus, with/without read/write delay, extended ALE
CLKOUT
t5
ALE
t16
t25
t6
t38 t17 t39 t27
t40
CSx
t6
A23-A16
(A15-A8) BHE
t17
Address
t27
Read Cycle BUS (P0)
t6
Address
t7
Data In
t8 t9
RD
t10 t11 t14 t15 t12 t13
t18 t19
Write Cycle BUS (P0)
Address
Data Out
t23 t8 t9
WR WRL WRH
t10 t11
t22
t13
t12
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 16 : External Memory Cycle: multiplexed bus, with/without read/write delay, normal ALE, read/ write chip select
CLKOUT
t5
ALE
t16
t25
t6
A23-A16
(A15-A8) BHE
t17
Address
t27
t16
Read Cycle BUS (P0)
t6
Address
t7
t51
Data In Address
t42
RdCSx
t44 t46 t48
t52
t49 t43
Write Cycle BUS (P0)
t45 t47 t56
Data Out
Address
t42
WrCSx
t50 t48 t49
t43
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 17 : External Memory Cycle: multiplexed bus, with/without read/write delay, extended ALE, read/ write chip select
CLKOUT
t5
ALE
t16
t25
t6
A23-A16
(A15-A8) BHE
t17
Address
t54
Read Cycle BUS (P0)
t6
Address
t7
Data In
t42 t43
RdCSx
t44 t45 t46 t48 t47 t49
t18 t19
Write Cycle BUS (P0)
Address
Data Out
t42 t43
WrCSx
t44 t45 t50
t56
t48 t49
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.10 - Demultiplexed bus VDD = 5V 10%, VSS = 0V, TA = -40 to +125C CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF, CL (for Port 6, CS) = 100pF ALE cycle time = 4 TCL + 2tA + tC + tF (80ns at 25MHz CPU clock without wait states) Table 19 : Demultiplexed bus characteristics
Max. CPU Clock = 25MHz Min. t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t201 t211 t22 t24 t26 t28 t38 t39 t41 t42 CC CC CC CC CC CC SR SR SR SR SR SR ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address/Unlatched CS to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1) Data float after RD rising edge (no RW-delay 1) Data valid to WR Data hold after WR ALE rising edge after RD, WR Address/Unlatched CS hold after RD, WR 2 ALE falling edge to Latched CS Latched CS low to Valid Data In Latched CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) 10 + tA 4 + tA 10 + tA -10 + tA 30 + tC 50 + tC - - - - 0 - Max. - - - - - - 20 + tC 40 + tC 40 + tA + tC 50 + 2tA + tC - 26 + tF Variable CPU Clock 1/2TCL = 1 to 25MHz Min. TCL - 10+ tA TCL - 16+ tA TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - Max. - - - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF + 2tA2 - TCL - 10 + tF + 2tA2 2TCL- 20 + tC TCL - 10+ tF -10 + tF 0 + tF -4 - tA - TCL - 14 + tF TCL - 4 + tA - - - - 10 - tA 3TCL - 20 + tC + 2tA - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
SR
-
10 + tF
CC CC CC CC CC SR CC CC
20 + tC 10 + tF -10 + tF 0 + tF -4 - tA - 6 + tF 16 + tA
- - - - 10 - tA 40 + tC+ 2tA - -
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ST10C167
Table 19 : Demultiplexed bus characteristics (continued)
Max. CPU Clock = 25MHz Min. t43 t46 t47 t48 t49 t50 t51 t531 t681 t55 t57 CC SR SR CC CC CC SR SR SR CC CC ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS -4 + tA - - 30 + tC 50 + tC 26 + tC 0 - - -10 + tF 6 + tF Max. - 16 + tC 36 + tC - - - - 20 + tF 0 + tF - - Variable CPU Clock 1/2TCL = 1 to 25MHz Min. -4 + t A - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - - -10 + tF TCL - 14 + tF Max. - 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
Notes 1. Guaranteed by design characterization. 2. RW-delay and tA refer to the next following bus cycle. 3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 18 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE
CLKOUT
t5
ALE
t16
t26
t6 t38
CSx
t17 t39
t41 t41u
t6
A23-A16
(A15-A8) BHE
t17
Address
t28
Read Cycle Data Bus (P0)
t18
Data In
t80 t81
RD
t14 t15 t21
t20
t12 t13
Write Cycle Data Bus (P0)
Data Out
t80 t81
WR WRL WRH
t22
t24
t12 t13
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 19 : External Memory Cycle: demultiplexed bus, with/without read/write delay, extended ALE
CLKOUT
t5
ALE
t16
t26
t6 t38 t17 t39
CSx
t41 t28
t6
A23-A16
(A15-A8) BHE
t17
Address
t28
Read Cycle Data Bus (P0)
t18
Data In
t80 t81
RD
t14 t15 t21
t20
t12
Write Cycle Data Bus (P0)
t13
Data Out
t80 t81
WR WRL WRH
t22
t24
t12 t13
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 20 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE, read/ write chip select
CLKOUT
t5
ALE
t16
t26
t6
A23-A16
(A15-A8) BHE
t17
Address
t55
Read Cycle Data Bus (P0)
t51
Data In
t82 t83
RdCsx
t46 t47
t53 t68
t48 t49
Write Cycle Data Bus (P0)
Data Out
t82 t83
WrCSx
t50
t57
t48 t49
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 21 : External Memory Cycle: demultiplexed bus, with/without read/write delay, extended ALE, read/write chip select
CLKOUT
t5
ALE
t16
t26
t6
A23-A16
(A15-A8) BHE
t17
Address
t55
Read Cycle Data Bus (P0)
t51
Data In
t82 t83
RdCsx
t46 t47 t68
t53
t48 t49
Write Cycle Data Bus (P0)
Data Out
t82 t83
WrCSx
t50
t57
t48 t49
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.11 - CLKOUT and READY VDD = 5V 10%, VSS = 0V, TA = -40 to +125C CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF CL (for Port 6, CS) = 100pF Table 20 : CLKOUT and READY characteristics
Max. CPU Clock = 25MHz Min. t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC CC CC CC CC CC SR SR SR SR SR SR CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1 Asynchronous READY hold time 1 Async. READY hold time after RD, WR high (Demultiplexed Bus) 2 40 14 10 - - 0 + tA 14 4 54 14 4 0 Max. 40 - - 4 4 10 + tA - - - - - 0 + 2t A + tC + tF 2 Variable CPU Clock 1/2TCL = 1 to 25MHz Min. 2TCL TCL - 6 TCL - 10 - - 0 + tA 14 4 2TCL + 14 14 4 0 Max. 2TCL - - 4 4 10 + tA - - - - - TCL - 20 + 2tA + tC + tF 2 ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
Notes 1.These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) Figure 22 : CLKOUT and READY
Running cycle 1) READY waitstate MUX/Tristate 6)
t32
CLKOUT
t33 t30 t34 t31 t29
ALE
7)
Command RD, WR
2)
t35
Sync
t36
t35
3)
t36
READY t58
Async
3)
t59
3)
t58
3)
t59
t604)
READY
t37
5)
Notes 1. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the traili ng (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7. The next external bus cycle may start here.
6)
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XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.12 - External bus arbitration VDD = 5V 10%, VSS = 0V, TA = -40 to +125C CL (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF CL (for Port 6, CS) = 100pF Table 21 : External bus arbitration
Max. CPU Clock = 25MHz Min. Max. - 20 20 20 24 20 24 Variable CPU Clock 1/2TCL = 1 to 25MHz Min. 20 - - - -4 - -4 Max. - 20 20 20 24 20 24 ns ns ns ns ns ns ns
Symbol
Parameter
Unit
t61 t62 t63 t64 t65 t66 t67
Note
SR CC CC CC CC CC CC
HOLD input setup time to CLKOUT CLKOUT to HLDA hig or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive
20 - - -1 -4 -1 -4
1. Guaranteed by design characterization.
Figure 23 : External bus arbitration, releasing the bus
CLKOUT
t61 HOLD t63 HLDA
1)
t62 BREQ t64
3) 2)
CSx (On P6.x)
Other Signals 1)
t66
Notes 1. The ST10C167 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pullup) after t64.
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XX - ELECTRICAL CHARACTERISTICS (continued) Figure 24 : External bus arbitration, (regaining the bus) CLKOUT t61 HOLD HLDA t62 BREQ t62
1) 2)
t62
t63
t65 CSx (On P6.x) Other Signals
Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence.Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10C167 requesting the bus. 2. The next ST10C167 driven bus cycle may start here.
t67
XX.4.13 - High-speed synchronous serial interface (SSC) timing Master mode VCC = 5V 10%, VSS = 0V, CPU clock = 25MHz, TA = -40 to +125C, CL = 100pF
Symbol Parameter SSC clock cycle time SSC clock high time SSC clock low time SSC clock rise time SSC clock fall time Write data valid after shift edge Write data hold after shift edge Read data setup time before latch edge, phase error detection on (SSCPEN = 1) Read data hold time after latch edge, phase error detection on (SSCPEN = 1) Read data setup time before latch edge, phase error detection off (SSCPEN = 0) Read data hold time after latch edge, phase error detection off (SSCPEN = 0) Max. Baud rate = 6.25M Baud ( = 0001h) Min. Max. 160 - - 10 10 15 - - Variable Baud rate (=0001h-FFFFh) Min. 8 TCL Max. 262144 TCL - - 10 10 15 - - ns ns ns ns ns ns ns ns Unit
t300 t301 t302 t303 t304 t305 t3061 t307p t308p t307 t308
Note
CC CC CC CC CC CC CC SR
160 70 70 - - - -2 60
t300/2 - 10 t300/2 - 10
- - - -2 2TCL+20
SR
4TCL
-
4TCL
-
ns
SR
40
-
40
-
ns
SR
0
-
0
-
ns
1. timing guaranteed by design.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) The formula for SSC Clock Cycle time is : t300 = 4 TCL * ( + 1) Where represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. Figure 25 : SSC master timing
t300
1)
t301
t302
2)
SCLK
t304 t305
MTSR
1st Out Bit
t305
2nd Out Bit
t303 t306
t305
Last Out Bit
t307 t308
MRST
1st.In Bit 2nd.In Bit
t307 t308
Last.In Bit
Notes 1. The phase and polarity of shift and latch edge of SCLK is programmable.This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received.
Slave mode VCC = 5V 10%, VSS = 0V, CPU clock = 25MHz, TA = -40 to +125C, CL = 100pF
Max Baud rate=6.25MBd ( = 0001h) Min. Max. 160 - - 10 10 54 - - - - - Variable Baud rate (=0001h-FFFFh ) Min. 8 TCL Max. 262144 TCL - - 10 10 2 TCL + 14 - - - - - ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
t310 t311 t312 t313 t314 t315 t316 t317p t318p t317 t318
Note
SR SR SR SR SR
SSC clock cycle time SSC clock high time SSC clock low time SSC clock rise time SSC clock fall time
160 70 70 - - - 0 100 140 10 0
t310/2 - 10 t310/2 - 10
- - - 0 4TCL + 20 6TCL + 20 10 0
CC Write data valid after shift edge CC Write data hold after shift edge SR SR SR SR
Read data setup time before latch edge, phase error detection on (SSCPEN = 1) Read data hold time after latch edge, phase error detection on (SSCPEN = 1) Read data setup time before latch edge, phase error detection off (SSCPEN = 0) Read data hold time after latch edge, phase error detection off (SSCPEN = 0)
1. Timing guaranteed by design.
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ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued) The formula for SSC Clock Cycle time is: t310 = 4 TCL * ( + 1) Where represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. Figure 26 : SSC slave timing
1)
t310
t311
t312
2)
SCLK
t314 t315
MRST
1st Out Bit
t313 t316
2nd Out Bit
t315
t315
Last Out Bit
t317 t318
MTSR
1st.In Bit 2nd.In Bit
t317 t318
Last.In Bit
Notes 1. The phase and polarity of shift and latch edge of SCLK is programmable.This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received.
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ST10C167
XXI - PACKAGE MECHANICAL DATA Figure 27 : Package Outline PQFP144 (28 x 28mm)
A A2 144 e A1 109 0,10 mm .004 inch
SEATING PLANE
1
108 B
36
73
E3 E1 E
37
D3 D1 D
72
c
L1
Dimensions Minimum A A1 A2 B c D D1 D3 e E E1 L L1 K
Note
Millimeters 1 Typical Maximum 4.07 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 30.95 27.90 0.65 31.20 28.00 0.80 1.60 0 (Min.), 7 (Max.) 31.45 28.10 0.95 1.219 1.098 0.026 3.42 3.67 0.38 0.23 31.45 28.10 0.010 0.125 0.009 0.005 1.219 1.098 Minimum
L K
Inches (approx) Typical Maximum 0.160 0.133 0.144 0.015 0.009 1.228 1.102 0.896 0.026 1.228 1.102 0.031 0.063 1.238 1.106 0.037 1.238 1.106
1. Package dimensions are in mm. The dimensions quoted in inches are rounded.
XXII - ORDERING INFORMATION
Salestype ST10C167-Q3/XX 1 ST10C167-Q6/XX 1
Note XX : ROM code identification characters
Temperature Range -40C to 125C -40C to 85C
Package PQFP144 (28 x 28mm) PQFP144 (28 x 28mm)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st .com
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